1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof. Particularly, the present invention relates to a semiconductor device having a multilayer interconnection structure of a buried interconnection, and a fabrication method thereof.
2. Description of the Background Art
As the first conventional art of a semiconductor device having a multilayer interconnection structure of a buried interconnection, the semiconductor device disclosed in Japanese Patent Laying-Open No. 9-153545 is taken by way of example. A fabrication method thereof will be described with reference to FIG. 20. Referring to FIG. 20, an interlayer insulation film 102 such as a silicon oxide film is formed by CVD (chemical vapor deposition) on a silicon substrate 101. A lower interconnection 104 is formed on interlayer insulation film 102.
A connection hole stopper film 106 such as a silicon nitride film is formed on interlayer insulation film 102 to cover lower interconnection 104. A lower interlayer insulation film 108 such as a silicon oxide film is formed by CVD and the like on connection hole stopper film 106. Then, an upper trench stopper film 109 such as a silicon nitride film is formed on lower interlayer insulation film 108.
Referring to FIG. 21, a resist pattern 112 is formed on upper trench stopper film 109. Using resist pattern 112 as a mask, upper trench stopper film 109 is subjected to anisotropic etching, whereby a connection hole 113a is formed. Then, resist pattern 112 is removed.
Referring to FIG. 22, an upper interlayer insulation film 110 such as a silicon oxide film is formed by CVD and the like on upper trench stopper film 109 to fill connection hole 13a. 
Referring to FIG. 23, a resist pattern 116 is formed on upper interlayer insulation film 110. Using resist pattern 116 as a mask, upper interlayer insulation film 110 is subjected to anisotropic etching, whereby an upper interconnection trench 118 that exposes the surface of upper trench stopper film 109 is formed.
By connection hole 113a formed in upper trench stopper film 109, lower interlayer insulation film 109 is etched at the same time in self-alignment, whereby a connection hole 113b that exposes the surface of connection hole stopper film 106 is formed. Then, resist pattern 116 is removed. By removing connection hole stopper film 106 exposed at the bottom of connection hole 113b, connection hole 113 that exposes the surface of lower interconnection 104 is formed.
Referring to FIG. 24, a conductive layer 120 to establish an upper interconnection is formed on upper interlayer insulation film 110 to fill connection hole 113 and upper interconnection trench 118. Referring to FIG. 25, a CMP (chemical mechanical polishing) process or the like is applied to conductive layer 120, whereby the conductive layer located above the top surface of upper interlayer insulation film 110 is removed to form an upper interconnection 120 in upper interconnection trench 118. Thus, the main part of the multilayer interconnection structure of a buried interconnection is completed in a semiconductor device.
As the second conventional art, the semiconductor device disclosed in Japanese Patent Laying-Open No. 8-335634 is taken by way of example. The fabrication method thereof will be described hereinafter. Referring to FIG. 26, a lower interconnection 104 is formed on a silicon substrate 101. An interlayer insulation film 122 such as a silicon oxide film is formed by CVD or the like on silicon substrate 101 to cover lower interconnection 104. A resist pattern 123 is formed on interlayer insulation film 122.
Referring to FIG. 27, interlayer insulation film 122 is subjected to anisotropic etching with resist pattern 123 as a mask, whereby a connection hole 124 that exposes the surface of lower interconnection 104 is formed. Referring to FIG. 28, an organic compound layer 125 is applied on interlayer insulation film 122 to fill connection hole 124. Desirably, the etching rate of organic compound layer 125 by anisotropic etching in forming an interconnection trench described afterwards is not more than xc2xd the etching rate of interlayer insulation film 122.
Referring to FIG. 29, organic compound layer 125 located above the top surface of interlayer insulation film 122 is removed, so that organic compound layer 125 remains only in connection hole 124.
Referring to FIG. 30, a resist pattern 126 is formed on interlayer insulation film 122. Referring to FIG. 31, interlayer insulation film 122 is subjected to anisotropic etching with resist pattern 126 as a mask, whereby an upper interconnection trench 118 of a predetermined depth is formed. Referring to FIG. 32, resist pattern 136 and organic compound layer 125 are removed at the same time.
Referring to FIG. 33, a conductive layer (not shown) that becomes the upper interconnection is formed on interlayer insulation film 122 to fill connection hole 124 and upper interconnection trench 118. By applying a CMP process to that conductive layer, the conductive layer located above the top surface of interlayer insulation film 122 is removed, whereby an upper interconnection 120 is formed in upper interconnection trench 118. Thus, the main part of the multilayer interconnection structure of a buried interconnection is completed in a semiconductor device.
The conventional semiconductor device obtained by the abovedescribed fabrication method has problems set forth in the following. The problem of the first conventional art is first described. In the actual device, another upper interconnection (not shown) is located in the proximity of upper interconnection 120 shown in FIG. 25. The two adjacent upper interconnections are both formed right above upper trench stopper film 109. Upper interlayer insulation film 110 is located between respective side surfaces facing each other of the two upper interconnections.
The capacitance between the two adjacent upper interconnections includes the capacitance of upper trench stopper film 109 in addition to the capacitance of upper interlayer insulation film 110. This increase in the capacitance between the interconnections causes degradation in the performance of the semiconductor device.
When an upper layer interconnection (not shown) is to be further provided on upper interconnection 120, a stopper film (not shown) such as a silicon nitride film must be additionally formed right above upper interconnection 120. This means that the capacitance of this stopper film is added to the capacitance between the two adjacent upper interconnections. As a result, the capacitance between the upper interconnections is further increased.
The problem of the second conventional art will be described hereinafter. Upper interconnection trench 118 filled with the upper interconnection is formed in interlayer insulation film 122 at the step shown in FIG. 31. When an upper interconnection trench differing in width from that of upper interconnection trench 118 is to be formed, there is a possibility that the upper interconnection trench of the smaller width will be formed with a depth smaller than that of an upper interconnection trench having a larger trench width. The depth of the upper interconnection trench may vary according to the trench width. This causes variation in the resistance of the upper interconnection filling the upper interconnection trench.
In view of the foregoing, an object of the present invention is to provide a semiconductor device aimed to reduce interconnection capacitance and variation in interconnection resistance.
Another object of the present invention is to provide a method of fabricating such a semiconductor device.
According to an aspect of the present invention, a semiconductor device includes a semiconductor substrate having a main surface, a first interconnection, an etching stopper film, a first insulation film, a second insulation film, an insulation trench, and a second interconnection. The first interconnection is formed on the semiconductor substrate. The etching stopper film is formed to directly cover the first interconnection. The first insulation film is formed to directly cover the etching stopper film. The second insulation is formed to directly cover the first insulation film. The interconnection trench is formed in the second insulation film to expose the surface of the first insulation film. The second interconnection is formed in that interconnection trench.
According to this semiconductor device, the etching stopper film generally formed of a silicon nitride film and the like is provided only right above the first interconnection. The etching stopper film is not present right under the second interconnection as in the conventional semiconductor device. Therefore, the capacitance according to the etching stopper film does not have to be taken into account in the capacitance of the two adjacent second interconnections. Only the capacitance according to the second insulation film is to be mainly considered. Thus, the capacitance between the two adjacent second interconnections can be reduced than that of the conventional semiconductor device due to the absence of an etching stopper film right under the second interconnection.
Preferably, the second insulation film has a predetermined thickness, and differs from the first insulation film in the etching property.
In this case, the second insulation film can be etched without substantially etching the first insulation film in the formation of the interconnection trench by applying anisotropic etching to the second insulation film. Therefore, the depth of the interconnection trench is substantially constant. Thus, variation in the resistance of the second interconnection formed in the interconnection trench can be reduced.
Specifically, a silicon oxide film formed by plasma CVD can be employed as the above first insulation film. A silicon oxide film formed by a spin-on-glass process can be employed as the second insulation film. A silicon nitride film can be employed as the etching stopper film.
According to another aspect of the present invention, a semiconductor device includes a semiconductor substrate having a main surface, a first interconnection, a conductive etching stopper film, a first insulation film, a second insulation film, a third insulation film, an interconnection trench, and a second interconnection. The first interconnection is formed on the semiconductor substrate. The conductive etching stopper film is formed to directly cover the first interconnection. The insulation film is formed to directly cover the conductive etching stopper film. The second insulation film is formed to directly cover the first insulation film, and has an etching property differing from that of the first insulation film. The third insulation film is formed to directly cover the second insulation film. The interconnection trench is formed in the third insulation film to expose the surface of the second insulation film. The second insulation film is formed in the interconnection trench.
According to this semiconductor device, the conductive etching stopper film is provided only right above the first interconnection. An etching stopper such as a silicon nitride film is not present right under the second interconnection as in the conventional semiconductor device. Therefore, the capacitance corresponding to the etching stopper film does not have to be taking into account in the capacitance of two adjacent second interconnections. Mainly the capacitance corresponding to the third insulation film is to be taken into consideration. Thus, the capacitance between two adjacent second interconnections can be reduced than that of the conventional semiconductor device due to the absence of an etching stopper film right under the second interconnection.
Preferably, the third insulation film has a predetermined thickness, and differs from the second insulation film in etching property.
When the interconnection trench is to be formed by applying anisotropic etching to the third insulation film, the third insulation film can be etched without substantially etching the second insulation film. Therefore, the depth of the interconnection trench becomes substantially constant. Thus, variation in the resistance of the second interconnection formed in that interconnection trench can be reduced.
Specifically, a silicon oxide film formed by the spin-on-glass process can be employed as the above third insulation film. A silicon oxide film formed by plasma CVD can be employed as the second insulation film.
Furthermore, a copper interconnection can be employed as the first interconnection and the second interconnection.
According to a further aspect of the present invention, a fabrication method of a semiconductor device includes the steps of: forming a first interconnection on a semiconductor substrate having a main surface, forming an etching stopper film to directly cover the first interconnection, forming a first insulation film to directly cover the etching stopper film, forming a second insulation film of a predetermined thickness differing from the first insulation in etching property to directly cover the first insulation film, forming a resist pattern on the second insulation film, forming an interconnection trench exposing the surface of the first insulation film by applying anisotropic etching to the second insulation film with the resist pattern as a mask, and forming a second interconnection in that interconnection trench.
According to this fabrication method, an etching stopper film such as a silicon nitride film is formed only right above the first interconnection. An etching stopper is not formed right under a second interconnection as in a conventional semiconductor device. Therefore, the capacitance between adjacent interconnections can be reduced than that of the conventional semiconductor device due to the absence of an etching stopper film right under the second interconnection. Since an etching stopper film does not have to be formed right under the second interconnection, the number of steps of the fabrication can be reduced.
Preferably, the etching rate of the first insulation film by the anisotropic etching in forming an interconnection trench is not more than xc2xd the etching rate of the second insulation film.
In this case, the second insulation film can be etched without substantially etching the first insulation film. As a result, the depth of the interconnection trench is substantially constant. Thus, variation in the resistance of the second interconnection formed in the interconnection trench can be reduced.
Preferably, the fabrication method includes the steps of forming a resist pattern on the first insulation film after formation of the first insulation film, forming an opening exposing the surface of the etching stopper film by applying anisotropic etching to the first insulation film with the resist pattern as a mask, and forming a connection hole to electrically connect the first and second interconnections by removing the etching stopper film exposed at the bottom of the opening to expose the surface of the first interconnection, after formation of the interconnection trench.
In this case, etching is to be carried out corresponding to only the thickness of the first insulation film as an opening for the formation of a connection hole. The film thickness of the resist pattern formed on the insulation film can be set thinner. As a result, the accuracy of photolithography to form the resist pattern can be improved.
Preferably, the etching rate of the etching stopper film by the anisotropic etching in forming an opening is not more than ⅕ the etching rate of the first insulation film.
In this case, damage on the first interconnection can be suppressed by virtue of the first insulation film being etched, without the etching stopper film being substantially etched in the formation of the opening. Furthermore, the first interconnection is not oxidized in removing the resist pattern used in the formation of an opening and in the formation of an interconnection trench by, for example, oxygen plasma.
Specifically, a silicon oxide film formed by plasma CVD can be employed as the above first insulation film. A silicon oxide film formed by the spin-on-glass process can be employed as the second insulation film.
According to still another aspect of the present invention, a fabrication method of a semiconductor device includes the steps of: forming a first interconnection on a semiconductor substrate having a main surface, forming a conductive etching stopper film to directly cover the first interconnection; forming a first insulation film to directly cover the conductive etching stopper film; forming a second insulation film to directly cover the first insulation film, differing in etching property from the first insulation film; forming a third insulation film of a predetermined thickness to directly cover the second insulation film, the etching property of the third insulation film differing from that of the second insulation film; forming an interconnection trench exposing the surface of the second insulation film by applying anisotropic etching on the third insulation film; and forming a second interconnection in that interconnection trench.
According to this fabrication method, the conductive etching stopper film is formed only right above the first interconnection. An etching stopper film such as of a silicon nitride film will not be formed right under the second interconnection as in a conventional semiconductor device. Therefore, the capacitance between two adjacent second interconnections can be reduced due to the absence of an etching stopper film right under the second interconnection, in comparison to the conventional semiconductor device. Since an etching stopper film does not have to be formed right under the second interconnection, the number of fabrication steps can be reduced.
Preferably, the etching rate of the second insulation film by anisotropic etching in forming the interconnection trench is not more than xc2xd the etching rate of the third insulation film.
In this case, the third insulation film can be etched without substantially etching the second insulation film. Therefore, the depth of the interconnection trench can be set substantially constant. Thus, variation in the resistance of the second interconnection formed within the interconnection trench can be reduced.
Preferably, the fabrication method includes the steps of forming a fourth insulation film to directly cover the third insulation film having an etching property differing from that of the third insulation film, and forming a connection hole in the first and second insulation films, electrically connecting the first and second interconnections. The step of forming a connection hole includes the steps of forming a resist pattern on the fourth insulation film, and forming a connection hole partially by applying anisotropic etching to the second insulation film partway with the resist pattern as a mask and forming a connection hole and exposing the surface of the conductive etching stopper film to by applying anisotropic etching simultaneously to the second insulation film or the first insulation film exposed at the bottom of the partially formed connection hole partway in the second insulation film, and to the third insulation film, in the formation of the interconnection trench in the third insulation film.
In this case, the connection hole is formed only partway in the second insulation film when the resist pattern on the fourth insulation film is removed by, for example, oxygen plasma. Therefore, the first interconnection can be prevented from being oxidized.
Specifically, a silicon oxide film formed by spin-on-glass process can be employed as the above first insulation film and third insulation film. A silicon oxide film formed by plasma CVD can be employed as the second insulation film and fourth insulation film.